D12320VF25V Datasheet, PDF (419/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 16-Bit Timer Pulse Unit (TPU)
Contention between TGR Read and Input Capture: If the input capture signal is generated in
the T₁ state of a TGR read cycle, the data that is read will be the data after input capture transfer.
Figure 9.53 shows the timing in this case.
φ
Address
TGR read cycle
T₁
T₂
TGR address
Read signal
Input capture
signal
TGR
X
M
Internal
M
data bus
Figure 9.53 Contention between TGR Read and Input Capture
Rev.7.00 Feb. 14, 2007 page 385 of 1108
REJ09B0089-0700