D12320VF25V Datasheet, PDF (1055/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

SMR1—Serial Mode Register 1
Appendix B Internal I/O Registers
H'FF80
SCI1
Bit
:
7
6
5
4
3
2
1
0
C/A
CHR
PE
O/E STOP MP
CKS1 CKS0
Initial value :
0
0
0
0
0
0
0
0
Read/Write : R/W
R/W R/W
R/W R/W
R/W
R/W R/W
Clock Select
0 0 φ clock
1 φ/4 clock
1 0 φ/16 clock
1 φ/64 clock
Multiprocessor Mode
0 Multiprocessor function
disabled
1 Multiprocessor format
selected
Stop Bit Length
0 1 stop bit
1 2 stop bits
Parity Mode
0 Even parity^*1
1 Odd parity^*2
Notes: 1.
2.
When even parity is selected, the parity bit added to
transmit data makes an even number of 1s in the
transmitted character and parity bit combined. Receive
data must have an even number of 1s in the received
character and parity bit combined.
When odd parity is selected, the parity bit added to
transmit data makes an odd number of 1s in the
transmitted character and parity bit combined. Receive
data must have an odd number of 1s in the received
character and parity bit combined.
Parity Enable
0 Parity bit addition and checking disabled
1 Parity bit addition and checking enabled*
Note: * When the PE bit is set to 1, the parity (even or odd) specified by
the O/E bit is added to transmit data before transmission. In
reception, the parity bit is checked for the parity (even or odd)
specified by the O/E bit.
Character Length
0 8-bit data
1 7-bit data*
Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted.
With 7-bit data, it is not possible to select LSB-first or MSB-first transfer.
Asynchronous Mode/Synchronous Mode Select
0 Asynchronous mode
1 Synchronous mode
Rev.7.00 Feb. 14, 2007 page 1021 of 1108
REJ09B0089-0700