D12320VF25V Datasheet, PDF (746/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 17 ROM
(c) Flash pass/fail parameter (FPFR: general register R0L of CPU)
An explanation of FPFR as the return value indicating the programming result is provided here.
Bit
:
7
6
5
4
3
2
1
0
0
MD
EE
FK
0
WD
WA
SF
Initial value : —
—
—
—
—
—
—
—
R/W
:—
R/W
R/W
R/W
—
R/W
R/W
R/W
Bit 7—Reserved: Returns 0.
Bit 6—Programming Mode Related Setting Error Detect (MD): Returns the check result of
whether the error protection state has been entered.
If the error protection state has been entered, 1 is written to this bit. This state can be confirmed by
checking bit 4, FLER, in the FCCS register. For conditions to enter the error protection state, see
section 17.25.3, Error Protection.
Bit 6
MD
0
1
Description
FLER setting is normal (FLER = 0)
FLER = 1, and programming cannot be performed
Bit 5—Programming Execution Error Detect (EE): 1 is returned to this bit when the specified
data could not be written because the user MAT was not erased.
If this bit is set to 1, there is a high possibility that the user MAT is partially rewritten. In this case,
after removing the error factor, erase the user MAT.
If FMATS is set to H'AA and the user boot MAT is selected, an error occurs when programming
is performed. In this case, both the user MAT and user boot MAT are not rewritten.
Programming of the user boot MAT should be performed in the boot mode or PROM mode.
Bit 5
EE
0
1
Description
Programming has ended normally
Programming has ended abnormally (programming result is not guaranteed)
Rev.7.00 Feb. 14, 2007 page 712 of 1108
REJ09B0089-0700