D12320VF25V Datasheet, PDF (995/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

TCR3—Timer Control Register 3
Appendix B Internal I/O Registers
H'FE80
TPU3
Bit
:
Initial value :
Read/Write :
7
CCLR2
0
R/W
6
CCLR1
0
R/W
5
CCLR0
0
R/W
4
3
CKEG1 CKEG0
0
0
R/W R/W
2
TPSC2
0
R/W
1
TPSC1
0
R/W
0
TPSC0
0
R/W
Timer Prescaler
0 0 0 Internal clock: counts on φ/1
1 Internal clock: counts on φ/4
1 0 Internal clock: counts on φ/16
1 Internal clock: counts on φ/64
1 0 0 External clock: counts on TCLKA pin input
1 Internal clock: counts on φ/1024
1 0 Internal clock: counts on φ/256
1 Internal clock: counts on φ/4096
Clock Edge
0 0 Count at rising edge
1 Count at falling edge
1 ⎯ Count at both edges
Counter Clear
Note: The internal clock edge selection is valid when the input clock is
φ/4 or slower. This setting is ignored if φ/1 or overflow/underflow
on another channel is selected as the input clock.
0 0 0 TCNT clearing disabled
1 TCNT cleared by TGRA compare match/input capture
1 0 TCNT cleared by TGRB compare match/input capture
1 _{TCNT cleared by counter clearing for another channel}
performing synchronous clearing/synchronous operation ^*1
1 0 0 TCNT clearing disabled
1 TCNT cleared by TGRC compare match/input capture ^*2
1 0 TCNT cleared by TGRD compare match/input capture ^*2
1 _{TCNT cleared by counter clearing for another channel}
performing synchronous clearing/synchronous operation ^*1
Notes: 1.
2.
Synchronous operation setting is performed by setting the SYNC
bit in TSYR to 1.
When TGRC or TGRD is used as a buffer register, TCNT is not
cleared because the buffer register setting has priority, and
compare match/input capture does not occur.
Rev.7.00 Feb. 14, 2007 page 961 of 1108
REJ09B0089-0700