D12320VF25V Datasheet, PDF (390/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 16-Bit Timer Pulse Unit (TPU)
Examples of Cascaded Operation: Figure 9.22 illustrates the operation when counting upon
TCNT2 overflow/underflow has been set for TCNT1, TGR1A and TGR2A have been designated
as input capture registers, and TIOC pin rising edge has been selected.
When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of
the 32-bit data are transferred to TGR1A, and the lower 16 bits to TGR2A.
TCNT1
clock
TCNT1
TCNT2
clock
H'03A1
TCNT2
H'FFFF
TIOCA1,
TIOCA2
TGR1A
H'03A2
H'0000
H'03A2
H'0001
TGR2A
H'0000
Figure 9.22 Example of Cascaded Operation (1)
Figure 9.23 illustrates the operation when counting upon TCNT2 overflow/underflow has been set
for TCNT1, and phase counting mode has been designated for channel 2.
TCNT1 is incremented by TCNT2 overflow and decremented by TCNT2 underflow.
Rev.7.00 Feb. 14, 2007 page 356 of 1108
REJ09B0089-0700