D12320VF25V Datasheet, PDF (415/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 16-Bit Timer Pulse Unit (TPU)
Contention between TCNT Write and Clear Operations: If the counter clear signal is
generated in the T₂ state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT
write is not performed.
Figure 9.49 shows the timing in this case.
TCNT write cycle
T₁
T₂
φ
Address
TCNT address
Write signal
Counter clear
signal
TCNT
N
H'0000
Figure 9.49 Contention between TCNT Write and Clear Operations
Rev.7.00 Feb. 14, 2007 page 381 of 1108
REJ09B0089-0700