D12320VF25V Datasheet, PDF (692/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 17 ROM
Write pulse application subroutine
Sub-routine write pulse
Enable WDT
Set PSU1 (2) bit in FLMCR1 (2)
Wait (y) μs
*6
Set P1 (2) bit in FLMCR1 (2)
Wait (z1) μs or (z2) μs or (z3) μs *5 *6
Clear P1 (2) bit in FLMCR1 (2)
Wait (α) μs
*6
Clear PSU1 (2) bit in FLMCR1 (2)
Wait (β) μs
*6
Disable WDT
End sub
Start of programming
Start
Set SWE1 (2) bit in FLMCR1 (2)
Wait (x) μs
*6
Store 128-byte program data in program
data area and reprogram data area
*4
n=1
Perform programming in the
erased state.
Do not perform additional
programming
on previously programmed
addresses.
m=0
Write 128-byte data in RAM reprogram _*1
data area consecutively to flash memory
Sub-routine-call
Write pulse
(z1) μs or (z2) μs
See Note *7 for pulse width
Set PV1 (2) bit in FLMCR1 (2)
Wait (γ) μs
*6
Note: 7. Write Pulse Width
*6
Number of Writes (n) Write Time (z) μs
1
z1
2
z1
3
z1
4
z1
5
z1
6
z1
7
z2
8
z2
9
z2
10
z2
11
z2
12
z2
1...3
z_...2
998
z2
999
z2
1000
z2
Note: Use a (z3) μs write pulse for additional
programming.
Increment address
H'FF dummy write to verify address
Wait (ε) μs
*6
Read verify data
*2
Read data = verify
NG
data?
OK
NG
6≥n?
OK
Additional program data computation
m=1
Transfer additional program data to
additional program data area
*4
Reprogram data computation
*3
Transfer reprogram data to reprogram _*4
data area
n←n+1
RAM
Program data area
(128 bytes)
Reprogram data area
(128 bytes)
128-byte
data verification
NG
completed?
OK
Clear PV1 (2) bit in FLMCR1 (2)
Wait (η) μs
*6
Additional program data
area (128 bytes)
NG
6≥n?
OK
Sequentially write 128-byte data in
additional program data area in RAM to *1
flash memory
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of
the first address written to must be H'00 or H'80. A 128-byte
data transfer must be performed even if writing fewer than 128
bytes; in this case, H'FF data must be written to the extra
Write Pulse
(z3) µs additional write pulse
*6
addresses.
2. Verify data is read in 16-bit (W) units.
3. Even bits for which programming has been completed in the
NG
m = 0?
*6
NG
n ≥ N?
128-byte programming loop will be subjected to additional
programming if they fail the subsequent verify operation.
4. A 128-byte area for storing program data, a 128-byte area for
OK
Clear SWE1 (2) bit in FLMCR1 (2)
OK
Clear SWE1 (2) bit in FLMCR1 (2)
storing reprogram data, and a 128-byte area for storing
additional program data should be provided in RAM. The
Wait (θ) μs
*6
Wait (θ) μs
*6
contents of the reprogram data and
additional program data areas are
modified as programming proceeds.
Program Data Operation Chart
End of programming
Programming failure
5. A write pulse of (z1) or (z2) μs should
Original Data (D) Verify Data (V)
Reprogram Data (X)
Comments
be applied according to the progress
0
0
1
Programming completed
of programming. See Note *7 for the
1
0
Programming incomplete; reprogram
pulse widths. When the additional
1
0
1
program data is programmed, a write
1
Still in erased state; no action
pulse of (z3) μs should be applied.
Reprogram data X' stands for
reprogram data to which a write pulse
has been applied.
6. For the values of x, y, z1, z2, z3, α, β,
γ, ε, η, θ, and N, see section 20.3.6,
Flash Memory Characteristics.
Additional Program Data Operation Chart
Reprogram Data (X') Verify Data (V) Additional Program Data (Y)
Comments
0
0
0
Additional programming executed
1
1
Additional programming not executed
1
0
1
Additional programming not executed
Additional programming not executed
Figure 17.45 Program/Program-Verify Flowchart
Rev.7.00 Feb. 14, 2007 page 658 of 1108
REJ09B0089-0700