D12320VF25V Datasheet, PDF (418/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 16-Bit Timer Pulse Unit (TPU)
Contention between Buffer Register Write and Compare Match: If a compare match occurs in
the T₂ state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the
data prior to the write.
Figure 9.52 shows the timing in this case.
φ
Address
Write signal
Compare
match signal
Buffer
register
TGR
TGR write cycle
T₁
T₂
Buffer register
address
Buffer register write data
N
M
N
Figure 9.52 Contention between Buffer Register Write and Compare Match
Rev.7.00 Feb. 14, 2007 page 384 of 1108
REJ09B0089-0700