82598EB Datasheet, PDF (99/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - PCIe
9:4
RO
000001b
10
RO
0b
11
RO
0b
12
HwInit 1b
14:13
RO
00b
15
RO
0b
Negotiated Link Width. Indicates the negotiated width of the link.
Relevant encodings for the 82598 are:
000001b = x1.
000010b = X2.
000100b = x4.
001000b = x8.
Link Training Error. Indicates that a link training error has occurred.
Link Training. Indicates that link training is in progress.
Slot Clock Configuration. When set, indicates that the 82598 uses the physical reference
clock that the platform provides at the connector. This bit must be cleared if the 82598
uses an independent clock. The Slot Clock Configuration bit is loaded from the
Slot_Clock_Cfg EEPROM bit.
Reserved. Read only as 00b.
Reserved.
The following registers are supported only if the capability version is two and above.
Device CAP 2 – 4 Byte, Offset 0xC4, (RO) – This register identifies the PCIe device-specific
capabilities. It is a read-only register with the same value for both LAN functions.
Bits
3:0
Bits
4
31:5
R/W
RO
R/W
RO
RO
Default
Description
1111b
Completion Timeout Ranges Supported. This field indicates the 82598’s support for the
optional completion timeout programmability mechanism.
Four time value ranges are defined:
• Range A: 50 μs to 10 ms.
• Range B: 10 ms to 250 ms.
• Range C: 250 ms to 4 s.
• Range D: 4 s to 64 s.
Bits are set according to the following values to show the timeout value ranges that the 82598
supports.
• 0000b = Completion timeout programming not supported. the 82598 must implement a
timeout value in the range of 50 μs to 50 ms.
• 0001b = Range A.
• 0010b = Range B.
• 0011b = Ranges A and B.
• 0110b = Ranges B and C.
• 0111b = Ranges A, B and C.
• 1110b = Ranges B, C and D.
• 1111b = Ranges A, B, C and D.
• All other values are reserved.
Default
Description
1b
Completion Timeout Disable Supported.
0b
Reserved.
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