82598EB Datasheet, PDF (127/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Power Up
• Firmware (FW) Reset – This reset is activated by writing a 1b to the FWR bit in the Host Interface
Control (HICR) register, or is being asserted by the firmware code or by the internal watchdog
expiration.
The resets affect the following registers and logic:
Table 3-37. 82598 Reset Effects
Reset Name
Reset Activation
EEPROM read (global)
EEPROM read (PCIe)
EEPROM read (per function)
LTSSM (back to detect/polling)
PCIe link data path
PCI configuration registers RO
PCI configuration registers R/W
Data path, memory space
MAC, PCS, auto negotiation
Wake up (PM) context
Wake up/manageability control/status
registers
Manageability unit
Strapping pins
Common Resets
Per Function Resets
Internal
Power
On
Reset or
LAN_
PWR_
GOOD
PE_
RST_N
In-
band
PCIe
Reset
D3hot?
D0
SW
Reset
Link
Reset
FW
Reset
Notes
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
2
X
X⁶
X⁶
X⁶
X⁶
X
X
X
1,3
X
4,5
X
X
X
X
X
1. If AUX_PWR = 0b the Wakeup Context is reset (PME_Status and PME_En bits should be 0b at reset
if the 82598 does not support PME from D3cold).
2. The following register fields do not follow the general rules previously stated:
a. SDP registers – reset on internal power on reset or LAN_PWR_GOOD only.
b. LED configuration registers
c. The Aux Power Detected bit in the PCIe Device Status register is reset on internal power on reset,
LAN_PWR_GOOD, and PE_RST_N only
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