82598EB Datasheet, PDF (68/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - PCIe
8. InitFC2-P
9. InitFC2-NP
10. InitFC2-Cpl
11. UpdateFC-P
12. UpdateFC-NP
Note: UpdateFC-Cpl is not sent because of the infinite FC-Cpl allocation.
3.1.1.10.3 Transmit EDB Nullifying
In the event of a retrain necessity, there is a need to guarantee that no abrupt termination of the Tx
packet happens. For this reason, early termination of the transmitted packet is possible. This is done by
appending the EDB to the packet.
3.1.1.11 PHY
3.1.1.11.1 Link Speed
The 82598 supports PCIe v2.0 (2.5 GT/s).
The 82598 does not initiate a hardware autonomous speed change and as a result the Hardware
Autonomous Speed Disable bit in the PCIe Link Control 2 register is hardwired to 0b.
The 82598 supports entering compliance mode at the speed indicated in the Target Link Speed field in
the PCIe Link Control 2 register.
3.1.1.11.2 Link Width
• The 82598 supports a maximum link width of x8, x4, x2, or x1 as determined by the EEPROM
Lane_Width field.
The maximum link width is loaded into the Maximum Link Width field of the PCIe Capability register
(LCAP[11:6]). The hardware default is the x8 link.
During link configuration, the platform and the 82598 negotiate on a common link width. The link width
must be one of the supported PCIe link widths (x1, 2x, x4, x8), such that:
• If Maximum Link Width = x8, then the 82598 negotiates to either x8, x4, x2 or x1¹
• If Maximum Link Width = x4, then the 82598 negotiates to either x4 or x1
• If Maximum Link Width = x1, then the 82598 only negotiates to x1
The 82598 does not initiate a hardware autonomous link width change and the Hardware Autonomous
Width Disable bit in the PCIe Link Control register is hardwired to 0b.
3.1.1.11.3 Polarity Inversion
If polarity inversion is detected the receiver must invert the received data.
During the training sequence, the receiver looks at symbols 6-15 of TS1 and TS2 as the indicator of
lane polarity inversion (D+ and D- are swapped). If lane polarity inversion occurs, the TS1 symbols 6-
15 received are D21.5 as opposed to the expected D10.2. Similarly, if lane polarity inversion occurs,
symbols 6-15 of the TS2 ordered set are D26.5 as opposed to the expected 5 D5.2. This provides the
clear indication of lane polarity inversion.
1. See restriction in Section 3.1.1.11.6.
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