82598EB Datasheet, PDF (115/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Non-Volatile Memory (EEPROM/Flash)
Accesses to the Flash are based on a direct decode of processor accesses to a memory window defined
in either:
• The 82598’s Flash Base Address register (PCIe Control register at offset 0x14 or 0x18).
• A certain address range of the IOADDR register defined by the IO Base Address register (PCIe
Control register at offset 0x18 or 0x20).
• The Expansion ROM Base Address register (PCIe Control register at offset 0x30).
The 82598 controls accesses to the Flash when it decodes a valid access.
Note:
Flash read accesses must always be assembled by the 82598 each time the access is greater
than a byte-wide access. The component byte reads or writes to the Flash take on the order
of 2 s; it continues to issue retry accesses during this time. The 82598 supports only byte
writes to the Flash.
Another way for software to access the Flash is directly using the Flash's 4-wire interface through the
Flash Access register (FLA). It can use this for reads, writes, or other Flash operations (accessing the
Flash status register, erase, etc.).
To directly access the Flash, software needs to:
• Write a 1b to the Flash Request bit (FLA.FL_REQ)
• Read the Flash Grant bit (FLA.FL_GNT) until it = 1b. It remains 0b as long as there are other
accesses to the Flash.
• Write or read the Flash using the direct access to the 4-wire interface as defined in the Flash
Access register (FLA). The exact protocol used depends on the Flash placed on the board and can
be found in the appropriate Flash datasheet.
• Write a 0b to the Flash Request bit (FLA.FL_REQ).
3.1.3.2.2 Flash Write Control
The Flash is write controlled by the FWE bits in the EEPROM/Flash Control and Data register (EEC.FWE).
Note that attempts to write to the Flash device when writes are disabled (FWE = 01b) should not be
attempted. Behavior after such an operation is undefined and can result in component and/or system
hangs.
After sending a one byte write to the Flash, software checks if it can send the next byte to write (check
if the write process in the Flash had finished) by reading the Flash Access register. If the bit
(FLA.FL_BUSY) in this register is set, the current write did not finish. If bit (FLA.FL_BUSY) is cleared,
then software can continue and write the next byte to the Flash.
3.1.3.2.3 Flash Erase Control
When software needs to erase the Flash, it sets bit FLA.FL_ER in the Flash Access register to 1b (Flash
Erase) and then set bit EEC.FWE in the EEPROM/Flash Control register to 0b.
Hardware gets this command and sends the erase command to the Flash. Note that the erase process
completes automatically. Software should wait for the end of the erase process before any further
access to the Flash. This can be checked by using the Flash Write control mechanism.
The op-code used for erase operation is defined in the FLASHOP register.
Sector erase by software is not supported. In order to delete a sector, the serial (bit bang) interface
should be used.
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