82598EB Datasheet, PDF (467/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - SMBus Troubleshooting Guide
16:2
3
LDFOT
24:3
1
GATI
0x0
RW
0x0
RW
Link down Fail-Over Time.
Defines the time (in seconds) the link should be down before doing a
fail-over to the second port.
This is also the time that the primary link should be up (after it was
down) before 82598EB will fail-over back to the primary port.
Gratuitous ARP Transmission Interval.
Defines the interval in seconds before retransmission of gratuitous ARP
packets.
5.3.12 SMBus Troubleshooting Guide
This section outlines the most common issues found while working with pass-through using the SMBus
sideband interface.
5.3.12.1 TCO Alert Line Stays Asserted After a Power Cycle
After the 82598EB resets both of its ports indicates a status change. If the BMC only reads status from
one port (slave address) the other one will continue to assert the TCO alert line.
Ideally, the BMC should use the ARA transaction (see Section 5.3.9) to determine which slave asserted
the TCO alert. Many customers only wish to use one port for manageability thus using ARA might not be
optimal.
An alternate to using ARA is to configure one of the ports to not report status and to set its SMBus
timeout period. In this case, the SMBus timeout period determines how long a port asserts the TCO
alert line awaiting a status read from a BMC; by default this value is zero, which indicates an infinite
timeout.
The SMBus configuration section of the EEPROM has a SMBus Notification Timeout (ms) field that can
be set to a recommended value of 0xFF (for this issue). Note that this timeout value is for both slave
addresses. Along with setting the SMBus Notification Timeout to 0xFF, it is recommended that the
second port be configured in the EEPROM to disable status alerting. This is accomplished by having the
Enable Status Reporting bit set to 0b for the desired port in the LAN configuration section of the
EEPROM.
The last solution for this issue is to have the BMC hard-code the slave addresses to always read from
both ports. As with the previous solution, it is also recommend that the second port have status
reporting disabled.
5.3.12.2 SMBus Commands are Always NACK'd by the 82598EB
There are several reasons why all commands sent to the 82598EB from a BMC could be NACK'd. The
following are the most common:
• Invalid EEPROM Image - The image itself might be invalid, or it could be a valid image; however,
it is not a pass-through image, as such SMBus connectivity is disabled.
• The BMC is not using the correct SMBus address - Many BMC vendors hard-code the SMBus
address(es) into their firmware. If the incorrect values are hard-coded, the 82598EB does not
respond.
—The SMBus address(es) can also be dynamically set using the SMBus ARP mechanism.
• The BMC is using the incorrect SMBus interface - The EEPROM might be configured to use one
physical SMBus port; however, the BMC is physically connected to a different one.
• Bus Interference - the bus connecting the BMC and the 82598EB might be unstable.
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