82598EB Datasheet, PDF (211/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Receive Functionality
Figure 3-19. Receive Data Flow
3.5.2 Receive Functionality
Packet reception consists of recognizing the presence of a packet on the wire, performing address
filtering and DMA queue assignment, storing the packet in the receive data FIFO, transferring the data
to assigned receive queues in host memory, and updating the state of a receive descriptor.
As a receive packet is accepted and processed, it is stored in on-die packet buffers before being
transferred to system memory. The 82598 supports up to eight separate packet buffers.
Each of the active packet buffers has one or more receive descriptor queues assigned to it. The
descriptor queues operate independently (but under a central arbitration scheme) to forward receive
packets from their packet buffers into system memory. The following section describes how the 82598's
receive descriptor queues are assigned.
The following operational modes impact allocation of receive descriptor queues:
• RSS (Receive Side Scaling) – RSS shares packet processing between several processor cores by
assigning packets into different descriptor queues. RSS assigns each packet an RSS output index.
See Section 3.5.2.10 for details on RSS.
• Virtual Machine Device queues (VMDq) – VMDq shares the 82598 DMA resources between more
than one software entity (operating system and/or software device driver). This is done through
replication of receive descriptor queues and their configuration registers. Current uses of VMDq
are for virtualized environments. VMDq assigns each packet a VMDq output index. See
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