82598EB Datasheet, PDF (369/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Register Descriptions
4.4.3.9.47 Broadcast Packets Transmitted Count – BPTC (0x040F4; R)
Field
BPTC
Bit(s)
Initial
Value
Description
31:0
0x0
Number of broadcast packets transmitted count.
This register counts the number of broadcast packets transmitted. It only increments if transmits are
enabled and counts all packets, including standard and secure packets (management packets are never
be more than 200 bytes).
After a broadcast packet is sent by the host, all flow control and manageability packets that are sent
are counted as Broadcast packets until a non-broadcast packet is sent by the host.
4.4.3.9.48 XSUM Error Count – XEC (0x04120; RO)
Field
XEC
Bit(s)
Initial
Value
Description
31:0
0x0
Number of receive IPv4, TCP, UDP checksum errors
XSUM errors are not counted when a packet has MAC error (CRC, length, under-size, over-size, byte
error or symbol error).
4.4.3.9.49 Receive Queue Statistic Mapping Registers RQSMR (0x2300 + 4*n
[n=0…15], RW)
These registers define the mapping of the receive queues to the per-queue statistics. This mapping
maps the queues to statistic registers QPRC and QBRC (note that there are 16 of each).
There are 64 queues and only 16 queue statistics registers so each entry refers to a queue and the
value indicates which QPRC and QBRC of the 16 this queue statistics is being counted.
Several queues can be mapped to a single statistic register. Each statistic register counts the number of
packets and bytes of all queues that are mapped to that statistics.
31
….24
Q_MAP[3]
…
23
16
Q_MAP[2]
…
15
8
Q_MAP[1]
…
7
0
Q_MAP[0]
…
... ... ...
…
Q_MAP[63]
…
Q_MAP[62]
…
Q_MAP[61]
…
Q_MAP[60]
369