82598EB Datasheet, PDF (66/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - PCIe
Table 3-7. Flow Control Credits Allocation
Credit Type
Posted Request Header (PH)
Posted Request Data (PD)
Non-Posted Request Header (NPH)
Non-Posted Request Data (NPD)
Completion Header (CPLH)
Completion Data (CPLD)
Operations
Target Write (1 unit)
Message (1 unit)
Target Write (Length/16 bytes = 1)
Message (1 unit)
Target Read (1 unit)
Configuration Read (1 unit)
Configuration Write (1 unit)
Configuration Write (1 unit)
Read Completion (N/A)
Read Completion (N/A)
Number of Credits
8 units (to enable concurrent accesses to
both LAN ports).
MAX_PAYLOAD_SIZE/16.
4 units (to enable concurrent target
accesses to both LAN ports).
4 units.
Infinite (accepted immediately).
Infinite (accepted immediately).
Rules for FC updates:
• The 82598 maintains two credits for NPD at any given time. It increments the credit by one after
a credit is consumed and sends an UpdateFC packet as soon as possible. UpdateFC packets are
scheduled immediately after a resource is available.
• The 82598 provides two credits for PH (such as, for two concurrent target writes) and two credits
for NPH (such as, for two concurrent target reads). UpdateFC packets are scheduled immediately
after a resource is available.
• The 82598 follows the PCIe recommendations for frequency of UpdateFC FCPs.
3.1.1.8.2 Upstream Flow Control Tracking
The 82598 issues a master transaction only when the required flow control credits are available. Credits
are tracked for posted, non-posted, and completions (the later to operate against a switch).
3.1.1.8.3 Flow Control Update Frequency
In all cases UpdateFC packets are scheduled immediately after a resource is available.
When the Link is in the L0 or L0s link state, Update FCPs for each enabled type of non-infinite flow
control credit must be scheduled for transmission at least once every 30 μs (-0% /+50%), except when
the Extended Sync bit of the Control Link register is set, in which case the limit is 120 μs (-0% /+50%).
3.1.1.8.4 Flow Control Timeout Mechanism
The 82598 implements the optional flow control update timeout mechanism.
The mechanism is active when the link is in L0 or L0s Link state. It uses a timer with a limit of 200 μs (-
0% /+50%), where the timer is reset by the receipt of any Init or Update FCP. Alternately, the timer
can be reset by the receipt of any DLLP.
Upon timer expiration, the mechanism instructs the PHY to retrain the link (using the LTSSM Recovery
state).
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