82598EB Datasheet, PDF (286/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Memory-Mapped Access to Expansion ROM
4.2.3 Memory-Mapped Access to Expansion ROM
External Flash can also be accessed as a memory-mapped expansion ROM. Accesses to offsets starting
from the expansion ROM base address reference the Flash provided that access is enabled through the
EEPROM Initialization Control Word and if the Expansion ROM Base Address register contains a valid
(non-zero) base memory address.
4.3
I/O-Mapped Access
All internal registers, memories, and Flash can be accessed using I/O operations. I/O accesses are
supported only if an I/O base address is allocated and mapped (BAR2 or BAR4), the BAR contains a
valid value, and I/O address decoding is enabled in PCIe configuration.
When an I/O BAR is mapped, the I/O address range allocated opens a 32-byte window in the system
I/0 address map. Within this window, two I/O addressable register are implemented: IOADDR and
IODATA. The IOADDR register is used to specify a reference to an internal register, memory, or Flash;
IODATA register is used as a window to the register, memory or Flash address specified by IOADDR.
Offset
0x00
0x04
0x08-0x1F
Abbreviation
IOADDR
IODATA
Reserved
Name
RW
Size
Internal register, internal memory, or Flash location
RW
4 bytes
address.
0x00000-0x1FFFF – Internal registers/memories
0x20000-0x7FFFF – Undefined
0x80000-0xFFFFF – Flash
Data field for reads or writes to the internal register,
RW
internal memory, or Flash location as identified by
the current value in IOADDR. All 32 bits of this
register have read/write capability.
4 bytes
Reserved
O
4 bytes
4.3.1 IOADDR (I/O Offset 0x00, RW)
IOADDR must always be written as a Dword access. Writes that are less than 32 bits are ignored. Reads
of any size return a Dword; however, the chipset or CPU might only return a subset of that Dword.
For software programmers, the IN and OUT instructions must be used to cause I/O cycles to be used on
the PCIe bus. Because writes must be to 32-bit, the source register of OUT must be EAX (the only 32-
bit register supported by the out command). For reads, the IN instruction can have any size target
register, but we recommended EAX be used.
Because only a particular range is addressable, the upper bits of this register are hard coded to zero.
Bits 31 through 20 are not write-able and always read back as 0b.
On hardware reset (Internal Power On Reset or LAN_PWR_GOOD) or PCI Reset, this register value
resets to 0x00000000. Once written, the value is retained until the next write or reset.
4.3.2 IODATA (I/O Offset 0x04, RW)
IODATA must always be written as a Dword access when the IOADDR register contains a value for
internal registers and memories (such as 0x00000-0x1FFFC). Writes less than 32 bits are ignored.
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