82598EB Datasheet, PDF (575/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Special Delay Requirements
8.8.3 Special Delay Requirements
The 82598 controller violates the DMTF NC-SI AC timing specification in terms of the hold (Thd) time
and minimum clock to output timing (Tco min), and needs special attention during the layout design.
To ensure the controller will be able to communicate with a specification-compliant BMC the following
guidelines must be followed:
• The clock traces from the clock source to the BMC and the one from the source to the 82598 have
to be length matched within 5 mils.
• Make sure there the total skew between the clocks at the input of the BMC and the 82598 is less
than 1 ns. This 1 ns should include the skew introduced by the clock buffer and by the difference
of input capacitance of the clock input buffers on the BMC and the 82598 respectively, as well as
any skew introduced by clock trace length differences.
• The delay introduced by the transmit and receive data lines should be equal, and not less than
0.3 ns. This translates to roughly two inches assuming 150 ps/inch propagation delay.
8.9
Connecting the MDIO Interfaces
The 82598 provides one MDIO interface for each LAN port to be used as configuration interface for an
external PHY attached to the controller.
Connect the MDIO and MDC signals to the corresponding pins on the PHY chip. Please make sure to
provide a pull up to 3.3 V dc on the MDIO signal.
8.10 Connecting the Software-Definable Pins (SDPs)
The controller has eight software-defined pins (SDP) per port that can be used for miscellaneous
hardware or software-controllable purposes. These pins and their function are bound to a specific LAN
device. These pins can each be individually configured to act as either input or output pins via EEPROM.
The initial value in case of an output can also be configured in the same way, however the silicon
default for any of these pins is to be configured as outputs.
To avoid signal contention, all eight pins are set as input pins until after EEPROM configuration has been
loaded.
Choose the right software definable pins for your applications keeping in mind that two of the eight
pins: SDPx_6 and SDPx_7 are open drain, the rest are tri-state buffers. Also take in consideration that
four of these pins (SDPx_0 – SDPx_3) can be used as general purpose interrupt (GPI) inputs. To act as
GPI pins, the desired pins must be configured as inputs. A separate GPI interrupt-detection enable is
then used to enable rising-edge detection of the input pin (rising-edge detection occurs by comparing
values sampled at 62.5 MHz, as opposed to an edge-detection circuit). When detected, a corresponding
GPI interrupt is indicated in the Interrupt Cause register.
When connecting the software definable pins to different digital signals please keep in mind that these
are 3.3 V signals and use level shifting if necessary.
The use, direction, and values of SDPs are controlled and accessed using fields in the Extended SDP
Control (ESDP) and Extended OD SDP Control (EODSDP).
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