82598EB Datasheet, PDF (274/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Interrupts
When used in conjunction with MSI-X interrupt vector, this feature enables interrupt cause recognition
and selective interrupt cause and mask bits reset without requiring software to read the EICR register.
As a result, the penalty related to a PCIe read transaction is avoided.
Extended Interrupt Auto Mask Enable register (EIAM)
Each bit in this register enables the setting of the corresponding bit in the EIMC register following a
write-to-clear to the EICR register or setting the corresponding bit in the EIMS register following a
write-to-set to EICS.
This register is provided in case MSI-X is not used, and therefore auto-clear through EIAC register is not
available.
In addition, when in MSI-X mode and GPIE.EIAME is set, software can set the bits of this register to
select mask bits that is reset during interrupt processing. In this mode, each bit in this register enables
setting of the corresponding bit in EIMC following interrupt generation.
3.5.4.2 Interrupt Moderation
An interrupt is generated upon receiving of incoming packets, as throttled by the EITR registers. There
are 16 EITR registers, each one is allocated to a vector of MSI-X.
When an MSI-X interrupt is activated, each active bit in EICR can trigger an interrupt vector. Allocating
MSI-X vectors is set by the setting of IVAR[23:0] registers. Following the allocation, the EITR
corresponding to the MSI-X vector is tied to the same allocation (EITR0 is allocated to MSI-X[0] and its
corresponding interrupts, EITR1 is allocated to MSI-X[1] and its corresponding interrupts etc.).
When MSI-X is not activated, the interrupt moderation is controlled by EITR[0].
Software can use EITR to limit the rate of delivery of interrupts to the host CPU. This register provides
a guaranteed inter-interrupt delay between interrupts asserted by the 82598, regardless of network
traffic conditions.
The following algorithm to convert the inter-interrupt interval value to the common interrupts/sec
performance metric:
Interrupts/sec = (256 * 10^-9sec * interval)^-1
For example, if the interval is programmed to 500d, the 82598 guarantees the CPU is not interrupted
by the 82598 for at least 128 s from the last interrupt. The maximum observable interrupt rate from
the 82598 should not exceed 7813 interrupts/sec.
Inversely, inter-interrupt interval value can be calculated as:
Inter-interrupt interval = (256 * 10^-9sec * interrupts/sec)^-1
The optimal performance setting for this register is very system and configuration specific.
The Extended Interrupt Throttle register should default to 0b upon initialization and reset. It loads in
the value programmed by the software after software initializes the device.
The 82598 implements interrupt moderation to reduce the number of interrupts software processes.
The moderation scheme is based on the EITR. Each time an interrupt event happens, the corresponding
bit in the EICR is activated. However, an interrupt message is not sent out on the PCIe interface until
the EITR counter assigned to the proper MSI-X vector that supports the EICR bit has counted down to
zero. The EITR counter is reloaded after it has reached zero with its initial value and the process repeats
again. The interrupt flow should follow the following diagram:
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