82598EB Datasheet, PDF (98/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - PCIe
Bits
1:0
R/W
R/W
Default
00b
2
RO
0b
3
R/W
0b
4
RO
0b
5
RO
0b
6
R/W
0b
7
R/W
0b
8
RO
0b
9
RO
Hardwired to
0b
11:10
RO
15:12
RO
00b
0000b
Description
Active State Link PM Control. This field controls the active state PM supported on the
link. Link PM functionality is determined by the lowest common denominator of all
functions. Bit 0 of this field is loaded from PCIe init configuration 1, offset 1, bit 15
(L0s Enable). Defined encodings are:
00b = PM disabled.
01b = L0s entry supported.
10b = Reserved.
11b = L0s and L1 supported.
Reserved.
Read Completion Boundary.
Link Disable. Not applicable for endpoint devices. Hardwired to 0b.
Retrain Clock. Not applicable for endpoint devices. Hardwired to 0b.
Common Clock Configuration. When set, indicates that the 82598 and the component
at the other end of the link are operating with a common reference clock. A value of
0b indicates that they are operating with an asynchronous clock. This parameter
affects the L0s exit latencies.
Extended Sync. When set, this bit forces an extended Tx of the FTS ordered set in FTS
and an extra TS1 at the exit from L0s prior to entering L0.
Reserved.
Hardware Autonomous Width Disable. When set to 1b, this bit disables hardware from
changing the link width for reasons other than attempting to correct an unreliable link
operation by reducing link width.
Reserved. Read only as 00b.
Reserved.
Link Status – 2 Byte, Offset 0xB2, (RO) – This register provides information about PCIe Link specific
parameters. This is a read only register identical to all functions.
Bits
3:0
R/W
RO
Default
0001b
Description
Current Link Speed. This field indicates the negotiated link speed of the given PCIe link.
Defined encodings are:
0001b = 2.5 Gb/s PCIe link.
0010b = 5 Gb/s PCIe link.
All other encodings are reserved.
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