82598EB Datasheet, PDF (11/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - General Information
1. General Information
1.1
Introduction
The Intel^® 82598EB 10 GbE Controller is a single, compact, low-power component with two fully
integrated Gigabit Ethernet Media Access Control (MAC) and XAUI ports.
The 82598EB supports 10GBASE-KX4/1000BASE-KX as in IEEE 802.3ap and CX4 (802.3ak). Ports also
contain a serializer-deserializer (designated “BX”) to support 1000Base-SX/LX (optical fiber) and GbE
backplane applications. CX4 and XAUI interfaces are also supported. In addition to managing MAC and
PHY Ethernet layer functions, the controller manages PCIe packet traffic across its transaction, link, and
physical/logical layers.
The 82598EB supports Intel’s Input/Output Acceleration Technology (I/OAT) v2.0. In addition, virtual
queues are supported by I/O virtualization.
The 82598EB’s on-board System Management Bus (SMBus) and Network Controller Sideband Interface
(NC-SI) ports enable network manageability implementations. With SMBus, management packets can
be routed to or from a management processor. SMBus ports enable industry standards, such as
Intelligent Platform Management Interface (IPMI). NC-SI ports enable support for the industry DMTF
standard.
The 82598EB, with PCIe architecture, is designed for high-performance and low host-memory access
latency. The 82598EB connects directly to a system Memory Control Hub (MCH) or I/O Controller Hub
(ICH) using one, two, four, or eight PCIe lanes.
Wide internal data paths eliminate performance bottlenecks by handling large address and data words.
Combining a parallel and pipelined logic architecture optimized for Ethernet and independent transmit
and receive queues, the 82598EB efficiently handles packets with minimum latency. The 82598EB
includes advanced interrupt handling features. It uses efficient ring buffer descriptor data structures,
with 32 Tx queues and 64 RX queues. Large on-chip buffers maintain superior performance. In
addition, using hardware acceleration, the 82598EB offloads tasks from the host, such as TCP/UDP/IP
checksum calculations and TCP segmentation.
The 82598EB package is a 31 mm x 31 mm, 883-ball, 1.0 mm ball pitch, Flip-Chip Ball Grid Array
(FCBGA).
1.2
Terminology and Acronyms
ACK
ARA
ARP
Acronym
Acknowledge.
SMBus Alert Response Address.
Address Resolution Protocol.
Description
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