82598EB Datasheet, PDF (210/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Device Data/Control Flows
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A packet enters the Rx MAC.
The MAC forwards the packet to the Rx filter.
If the packet matches the pre-programmed criteria of the Rx filtering, it is forwarded to the Rx FIFO.
The receive DMA fetches the next descriptor from the appropriate ring to be used for the next received packet.
Description
After the entire packet is placed into the Rx FIFO, the receive DMA posts the packet data to the location
indicated by the descriptor through the PCIe interface.
If the packet size is greater than the buffer size, more descriptors are fetched and their buffers are used for
the received packet.
When the packet is placed into host memory, the receive DMA updates all the descriptor(s) that were used by
the packet data.
The receive DMA writes back the descriptor content along with status bits that indicate the packet information
including what offloads were done on that packet.
The 82598 initiates an interrupt to the host to indicate that a new received packet is ready in host memory.
The host reads the packet data and sends it to the TCP/IP stack for further processing. The host releases the
associated buffer(s) and descriptor(s) once they are no longer in use.
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