82598EB Datasheet, PDF (100/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - PCIe
Device Control 2 – 2 Byte, Offset 0xC8, (RW) – This register controls the PCIe specific parameters.
Note that there is a dedicated register per each function.
Bits
R/W
3:0
RW
4
RW
15:5
RO
Default
Description
0b
Completion Timeout Value. For devices that support completion timeout programmability,
this field enables system software to modify the completion timeout value.
Defined encodings:
• 0000b = Default range: 50 μs to 50 ms.
Note: It is strongly recommended that the completion timeout mechanism not expire in less
than 10 ms.
Values available if Range A (50 μs to 10 ms) programmability range is supported:
• 0001b = 50 μs to 100 μs.
• 0010b = 1 ms to 10 ms.
Values available if Range B (10 ms to 250 ms) programmability range is supported:
• 0101b = 16 ms to 55 ms.
• 0110b = 65 ms to 210 ms.
Values available if Range C (250 ms to 4 s) programmability range is supported:
• 1001b = 260 ms to 900 ms.
• 1010b = 1 s to 3.5 s.
Values available if the Range D (4 s to 64 s) programmability range is supported:
• 1101b = 4 s to 13 s.
• 1110b = 17 s to 64 s.
Values not defined are reserved.
Software is permitted to change the value of this field at any time. For requests already
pending when the completion timeout value is changed, hardware is permitted to use either
the new or the old value for the outstanding requests and is permitted to base the start time
for each request either on when this value was changed or on when each request was issued.
0b
Completion Timeout Disable. When set to 1b, this bit disables the completion timeout
mechanism.
Software is permitted to set or clear this bit at any time. When set, the completion timeout
detection mechanism is disabled. If there are outstanding requests when the bit is cleared, it
is permitted but not required for hardware to apply the completion timeout mechanism to
the outstanding requests. If this is done, it is permitted to base the start time for each
request on either the time this bit was cleared or the time each request was issued.
0b
Reserved.
Link Control 2 – 2 Byte, Offset 0xD0, (RW)
Bits
R/W
3:0
RW
Default
See
description
Description
Target Link Speed. This field is used to set the target compliance mode speed when
software is using the Enter Compliance bit to force a link into compliance mode.
Defined encodings are:
0001b = 2.5 Gb/s target link speed.
0010b = 5 Gb/s target link speed.
All other encodings are reserved.
If a value is written to this field that does not correspond to a speed included in the
Supported Link Speeds field, the result is undefined.
The default value of this field is the highest link speed supported by the 82598 (as
reported in the Supported Link Speeds field of the Link Capabilities register) unless the
corresponding platform/form factor requires a different default value.
100