82598EB Datasheet, PDF (175/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Hardware EEPROM Sections
13
GIO Down Reset
0b
Disable
12
Lane Reversal
0b
Disable
11
Good Recovery
0b
10
Leaky Bucket Disable 1b
9:7
Reserved
0b
6
GIO TS Retrain Mode
0b
5
L2 Disable
0b
4
Skip Disable
0b
3
Reserved
0b
2
Electrical Idle
0b
1:0
Latency_To_Enter_L1 11b
Disables a core reset when the PCIe link goes down.
Disables the ability to negotiate a lane reversal.
When this bit is set, the LTSSM recovery states always progress towards linkup
(force a good recovery when recovery occurs).
Disables the leaky bucket mechanism in the PCIe PHY. Disabling this
mechanism holds the link from going to a recovery retrain in case of disparity
errors.
Reserved.
Controls the condition of an LTSSM entry to recovery.
Disables the link from entering the L2 state.
Disables the skip symbol insertion in the elastic buffer.
Reserved.
Electrical Idle Mask
If set to 1b, disables a check for an illegal electrical idle sequence (for example,
eidle ordered set without common mode and vise versa) and excepts any of
them as the correct eidle sequence.
Note: The specification can be interpreted so that the eidle ordered set is
sufficient for a transition to any of the power management states. The use of
this bit enables such interpretation and avoids the possibility of correct
behavior being understood as illegal sequences.
Period (in the L0s state) before transitioning into an L1 state.
00b = 64 μs.
01b = 256 μs.
10b = 1 ms.
11b = 4 ms.
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