82598EB Datasheet, PDF (92/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - PCIe
Table 3-29. MSI-X Table Structure (Vector Control Field)
Bits
31:1
Default
Type
0x00
R/W
0
1b
R/W
Description
Reserved. After reset, the state of these bits must be 0b.
However, for potential future use, software must preserve the value of these reserved
bits when modifying the value of other Vector Control bits. If software modifies the
value of these reserved bits, the result is undefined.
Mask Bit. When this bit is set, the function is prohibited from sending a message using
this MSI-X table entry. However, any other MSI-X table entries programmed with the
same vector are still capable of sending an equivalent message unless they are also
masked.
This bit’s state after reset is 1b (entry is masked).
This bit is read/write.
To request service using a given MSI-X table entry, a function performs a Dword memory write
transaction using the contents of the Message Data field entry for data, the contents of the Message
Upper Address field for the upper 32 bits of the address, and the contents of the Message Address field
entry for the lower 32 bits of the address. A memory read transaction from the address targeted by the
MSI-X message produces undefined results.
The MSI-X table and MSI-X PBA are permitted to co-reside within a naturally aligned 4 kB address
range, though they must not overlap with each other.
MSI-X table entries and Pending bits are each numbered 0 through N-1, where N-1 is indicated by the
Table Size field in the MSI-X Message Control register. For a given arbitrary MSI-X table entry K, its
starting address can be calculated with the formula:
Entry starting address = Table base + K*16
For the associated Pending bit K, its address for Qword access and bit number within that Qword can be
calculated with the formulas:
Qword address = PBA base + (K div 64)*8
Qword bit# = K mod 64
Software that chooses to read Pending bit K with Dword accesses can use these formulas:
Dword address = PBA base + (K div 32)*4
Dword bit# = K mod 32
3.1.1.14.7 PCIe Configuration Registers
PCIe provides two mechanisms to support native features:
• PCIe defines a PCI capability pointer indicating support for PCIe
• PCIe extends the configuration space beyond the 256 bytes available for PCI to 4096 bytes.
Initialization values of the Configuration registers are marked in parenthesis.
Color Notation:
Dotted – Fields that are identical to all functions
Light-blue – Read-only fields
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