82598EB Datasheet, PDF (278/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - 802.1q VLAN Support
address and data value, specified by a table that resides in memory space. However, most of the other
characteristics of MSI-X are identical to those of MSI. For more information on MSI-X, refer to the PCI
Local Bus Specification, Revision 3.0.
MSI-X maps each of the 82598 interrupt causes into an interrupt vector that is conveyed by the 82598
as a posted-write PCIe transaction. Mapping of an interrupt cause into an MSI-X vector is determined
by system software (device driver) through a translation table stored in the MSI-X allocation registers.
Each entry of the allocation registers define the vector for a single interrupt cause. Table 3-77 lists
which interrupt cause is represented by each entry in the MSI-X Allocation registers.
Table 3-77. Interrupt Cases for MSI-X
Interrupt
RxQ[63:0]
Entry¹
63:0
TxQ[31:0]
95:64
TCP Timer
96
Other causes
97
1. Entry in the MSI-X Allocation registers.
Description
Receive Queues
Associates an interrupt occurring in each of the Rx queues with a corresponding
entry in the MSI-X Allocation registers.
Transmit Queues
Associates an interrupt occurring in each of the Tx queues with a corresponding
entry in the MSI-X Allocation registers.
TCP Timer
Associates an interrupt issued by the TCP timer with a corresponding entry in the
MSI-X Allocation registers
Other Causes
Associates an interrupt issued by the other causes with a corresponding entry in
the MSI-X Allocation registers
Each MSI-X interrupt vector has some attributes assigned to it, such as the address and data for its
posted-write message.
3.5.5 802.1q VLAN Support
The 82598 provides several specific mechanisms to support 802.1q VLANs:
• Optional adding (for transmits) and ping strip (for receives) of IEEE 802.1q VLAN tags.
• Optional ability to filter packets belonging to certain 802.1q VLANs.
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