82598EB Datasheet, PDF (174/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Hardware EEPROM Sections
13
12
11:10
9
8
7:6
5
4
3:2
Bit
1
0
Ack_Nak_Sch
0b
Cache_Lsize
0b
GIO_Cap
10b
IO_Sup
1b
Packet_Size
1b
Lane_Width
11b
Elastic Buffer
0b
Diff1
Elastic buffer ctrl 0b
Act_Stat_PM_Su
p
Name
Slot_Clock_Cfg
11b
Default
1b
Loop Back
0b
Polarity Inversion
ACK/NAK Scheme
0b = Scheduled for transmission following any TLP.
1b = Scheduled for transmission according to timeouts specified in the PCIe
specification.
Cache Line Size
0b = 64 bytes.
1b = 128 bytes.
PCIe Capability Version
This field must be set to 10b to use extended configuration capability (used for
a timeout mechanism).
This bit is mapped to GCR.PCIe_Capability_Version.
I/O Support (effects I/O BAR request).
When set to 1b, I/O is supported.
Default Packet Size
0b = 128 bytes.
1b = 256 bytes.
Max Link Width
00b = 1 lane.
01b = 2 lanes.
10b = 4 lanes.
11b = 8 lanes.
When set to 1b, the elastic buffers are activated in a more limited mode (read
and write pointers distance wise).
When set to 1b, sets the elastic buffers to a mode that sets phase-only mode
during electrical-idle states.
Determines support for Active State Link Power Management (ASLPM). Loaded
into the PCIe Active State Link PM Support register.
Description
When set, 82598 uses the PCIe reference clock supplied on the connector (for
add-in solutions).
Checks the polarity inversion in a loop-back master entry.
3.4.3.3.5 PCIe Control – Offset 4
Bit
15
14
Name
Reserved
DLLP Timer Enable
Default
Description
0b
Reserved.
0b
When set, enables the DLLP timer counter.
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