82598EB Datasheet, PDF (388/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Register Descriptions
Reserved
FW_Val_bit
14:7
0x0
15
0b
Reset_cnt
Ext_err_ind
18:16
0x0
24:19
0x0
PCIe_config_
25
0b
err_ind
PHY_SerDes0_
26
0b
config_ err_ind
PHY_SerDes1_
27
0b
config_ err_ind
Unlock_EEP
28
0b
Reserved
31:29
0x0
Reserved
Firmware Valid Bit
Hardware clears this bit in reset de-assertion so software can know firmware mode
(bits 1-5) is invalid. Firmware should set it to 1b when it is ready (end of boot
sequence).
Reset counter firmware increments this field after every reset.
External Error Indication
Firmware writes here the reason that the firmware has reset/clock gated (EEPROM,
Flash, patch corruption, etc.).
Possible values:
0x00 = No Error.
0x01 = Invalid EEPROM checksum.
0x02 = Unlocked secured EEPROM.
0x03 = Clock off host command.
0x04 = Invalid Flash checksum.
0x05 = C0 checksum failed.
0x06 = C1 checksum failed.
0x07 = C2 checksum failed.
0x08 = C3 checksum failed.
0x09 = TLB table exceeded.
0x0A = DMA load failed.
0x0B = Bad hardware version in patch load.
0x0C = Flash device not supported in the 82598.
0x0D = Unspecified error.
0x3F = Reserved – maximum error value.
PCIe Configuration Error Indication
Set to 1b by firmware when it fails to configure PCIe interface.
Cleared by firmware upon successful configuration of PCIe interface.
PHY/SerDes0 Configuration Error Indication
Set to 1b by firmware when it fails to configure PHY/SerDes of LAN0.
Cleared by firmware upon successful configuration of PHY/SerDes of LAN0.
PHY/SerDes1 Configuration Error Indication
Set to 1b by firmware when it fails to configure PHY/SerDes of LAN1.
Cleared by firmware upon successful configuration of PHY/SerDes of LAN1.
Unlock EEPROM
Set to 1b by software in order to enable re-writing to the EEPROM at address 0x00
(EEPROM Control Word 1).
Cleared by firmware once EEPROM Control Word 1 is unlocked.
Reserved
Note:
This register should be written only by manageability firmware. The software device driver
should only read this register.
Firmware ignores the EEPROM semaphore in operating system hung states. Bits 15:0 are
cleared on firmware reset.
388