82598EB Datasheet, PDF (321/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Register Descriptions
EIAME
PBA_
support
30
0b
Extended Interrupt Auto Mask Enable
When set (usually in MSI-X mode); upon initializing an MSI-X message, bits set
in EIAM associated with this message is cleared. Otherwise, EIAM is used only
after a read or write of the EICR/EICS registers.
31
0b
PBA Support
When set, setting one of the extended interrupts masks via EIMS causes the
PBA bit of the associated MSI-X vector to be cleared. Otherwise, the 82598
behaves in a way supporting legacy INT-x interrupts.
Note: Should be cleared when working in INT-x or MSI mode and set in MSI-X
mode.
The 82598 allows for up to four externally controlled interrupts. The lower four software-definable pins,
SDP[3:0], can be mapped for use as GPI interrupt bits. The mappings are enabled by the SDPx_GPIEN
bits only when these signals are also configured as inputs using SDPx_IODIR.
When configured to function as external interrupt pins, a GPI interrupt is generated when the
corresponding pin is sampled in an active-high state. The bit mappings are listed in the following table
for clarity.
Table 4-5. GPI to SDP Bit Mappings
SDP pin to be used as GPI
ESDP Field Settings
Directionality
Enable as GPI interrupt
3
SDP3_IODIR
SDP3_GPIEN
2
SDP2_IODIR
SDP2_GPIEN
1
SDP1_IODIR
SDP1_GPIEN
0
SDP0_IODIR
SDP0_GPIEN
Resulting EICR bit
(GPI)
27
26
25
24
4.4.3.4 Flow Control Registers Description
4.4.3.4.1 Priority Flow Control Type Opcode – PFCTOP (0x03008; RW)
Field
FCT
FCOP
Bit(s)
Initial
Value
15:0
0x8808
31:16
0x0101
Description
Class-Based Flow Control Type
Class-Based Flow Control Opcode
This register contains the Type field hardware that is matched against a recognized class-based flow
control packet.
321