82598EB Datasheet, PDF (581/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Power Supply Filtering
8.14.1.1 Using Regulators With Enable Pins
The use of regulators with enable pins is very helpful in controlling sequencing. Connecting the enable
of the 1.8 V dc regulator to 3.3 V dc will allow the 1.8 V dc to ramp. Connecting the enable of the
1.2 V dc regulator to the 1.8 V dc output assures that the 1.2 V dc rail will ramp after the 1.8 V dc rail.
This provides a quick solution to power sequencing. Make sure to check design parameters for inputs
with this configuration. Alternatively power monitoring chips can be used to provide the proper
sequencing by keeping the voltage regulators with lower output in shutdown until the one immediately
above doesn’t reach a certain output voltage level.
8.14.2
Power Supply Filtering
These filters provide several high-frequency bypass capacitors for each power rail. Select values in the
range of 0.001 μF to 0.1 μF and, if possible, orient the capacitors close to the device and adjacent to
power pads.
Traces between decoupling and I/O filter capacitors should be as short and wide as practical. Long and
thin traces are more inductive and would reduce the intended effect of decoupling capacitors. Also for
similar reasons, traces to I/O signals and signal terminations should be as short as possible. Vias to the
decoupling capacitors should be sufficiently large in diameter to decrease series inductance.
Table 8-7. Minimum Number of Bypass Capacitors per Power Rail.
Power Rail
3.3 V dc
1.8 V dc
1.2 V dc
Total Bulk Capacitance
22 F
66 F
160 F
0.1μF
5
8
40
0.001μF
0
0
6
8.14.3 Support for Power Management and Wake Up
The designer must connect the MAIN_PWR_OK and the AUX_PWR signals on the board. These are
digital inputs to the 82598 controller and serve the following purpose:
The MAIN_PWR_OK will signal the 82598 controller that the main power from the system is up and
stable. For example it could be pulled up to the 3.3 V dc main rail, or connected to a power well signal
available in the system.
When sampled high AUX_PWR will indicate that auxiliary power is available to the controller, and
therefore the controller advertises D3cold Wake Up support. The amount of power required for the
function (which includes the entire network interface card) is advertised in the Power Management Data
Register, which is loaded from the EEPROM.
If wakeup support is desired, AUX_PWR needs to be pulled high and the appropriate wakeup LAN
address filters must also be set. The initial power management settings are specified by EEPROM bits.
When a wakeup event occurs the controller asserts the PE_WAKEn signal to wake the system up.
PE_WAKEn remains asserted until PME status is cleared in the 82598 Power Management Control/
Status Register.
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