82598EB Datasheet, PDF (85/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - PCIe
Table 3-16. Power Management Register Block
Byte Offset
0x40
0x44
Byte 3
Byte 2
Power Management Capabilities (PMC)
Data
PMCSR_BSE Bridge
Support Extensions
Byte 1
Byte 0
Next Pointer
Capability ID
Power Management Control/Status Register (PMCSR)
The following section describes the register definitions, whether they are required or optional for
compliance, and how they are implemented in the 82598.
Capability ID – 1 Byte, Offset 0x40, (RO) – This field equals 0x01 indicating the linked list item as
being the PCI Power Management register.
Next Pointer – 1 Byte, Offset 0x41, (RO) – This field provides an offset to the next capability item in
the capability list. Its value of0x50 points to MSI capability.
Power Management Capabilities (PMC) – 2 Byte, Offset 0x42, (RO) – This field describes the device
functionality during the power management states as listed in Table 3-17. Note that each device
function has its own register.
Table 3-17. Power Management Capabilities (PMC)
Bits
15:11
Default
01001b
10
0b
9
0b
8:6
000b
5
1b
4
0b
3
0b
2:0
011b
R/W
RO
RO
RO
RO
RO
RO
RO
RO
Description
PME_Support. This 5-bit field indicates the power states in which the function can
assert PME#. Its initial value is loaded from EEPROM word 0x0A.
Condition Functionality Values:
• No AUX Pwr PME at D0 and D3_hot = 01001b
• AUX Pwr PME at D0, D3_hot, and D3_cold = 11001b
D2_Support – 82598 does not support the D2 state.
D1_Support – 82598 does not support the D2 state.
AUX Current – Required current defined in the Data register.
DSI – 82598 requires its device driver to be executed following a transition to the D0
uninitialized state.
Reserved.
PME_Clock – Disabled. Hardwired to 0b.
Version – 82598 complies with the PCI PM specification revision 1.2.
Power Management Control/Status Register (PMCSR) – 2 Byte, Offset 0x44, (R/W) – This
register is used to control and monitor power management events in the device. Note that each device
function has its own PMCSR.
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