82598EB Datasheet, PDF (320/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Register Descriptions
4.4.3.3.11 MSI-X Pending Bit Array Clear – PBACL (0x11068, RW)
Field
PENBITCLR
Reserved
Bit(s)
19:0
31:20
Initial
Value
0x0
0x0
Description
MSI-X Pending Bits Clear
Writing 1b to any bit clears it’s content; writing 0b has no effect.
Reading this register returns the MSIPBA.PENBIT value.
Reserved
4.4.3.3.12 General Purpose Interrupt Enable – GPIE (0x00898, RW)
Field
SDP0_GPIEN
SDP1_GPIEN
SDP2_GPIEN
SDP3_GPIEN
MSIX_MODE
OCD
EIMEN
Reserved
Bit(s)
0
1
2
3
4
5
6
29:5
Initial
Value
0b
0b
0b
0b
0b
0b
0b
0x0
Description
General Purpose Interrupt Detection Enable for SDP0
If software-controllable IO pin SDP0 is configured as an input, this bit (when 1b)
enables use for GPI interrupt detection.
General Purpose Interrupt Detection Enable for SDP1
If software-controllable IO pin SDP1 is configured as an input, this bit (when 1b)
enables use for GPI interrupt detection.
General Purpose Interrupt Detection Enable for SDP2
If software-controllable IO pin SDP2 is configured as an input, this bit (when 1b)
enables use for GPI interrupt detection.
General Purpose Interrupt Detection Enable for SDP3
If software-controllable IO pin SDP3 is configured as an input, this bit (when 1b)
enables use for GPI interrupt detection.
MSIX Mode
0b = non-MSIX, IVAR map Rx/Tx causes to 16 EICR bits, but MSIX[0] is
asserted for all.
1b = MSIX mode, IVAR maps Rx/Tx causes to 16 EICR bits.
Other Clear Disable
When set indicates that only bits 20-29 of the EICR are cleared on read.
EICS Immediate Interrupt Enable
When set, setting bit in the EICS causes an immediate interrupt. If not set, the
EICS interrupt waits for EITR expiration
Reserved
320