82598EB Datasheet, PDF (230/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Receive Functionality
Note: The 82598 NEVER fetches descriptors beyond the descriptor TAIL pointer.
3.5.2.7 Receive Descriptor Write-Back
Processors have cache line sizes that are larger than the receive descriptor size (16 bytes).
Consequently, writing back descriptor information for each received packet would cause expensive
partial cache line updates. A receive descriptor packing mechanism minimizes the occurrence of partial
line write backs.
To maximize memory efficiency, receive descriptors are packed together and written as a cache line
whenever possible. Descriptor write backs accumulate and are opportunistically written out in cache
line-oriented chunks, under the following scenarios:
• RXDCTL.WTHRESH descriptors have been used (the specified maximum threshold of unwritten
used descriptors has been reached)
• The receive timer expires (ITR)
• Dynamic interrupt moderation (immediate bit indicating ITR should be overwritten)
When the number of descriptors specified by RXDCTL.WTHRESH have been used, they are written back,
regardless of cache line alignment. It is therefore recommended that WTHRESH be a multiple of cache
line size. When the receive timer (ITR) expires, all used descriptors are forced to be written back prior
to initiating the interrupt, for consistency.
When the 82598 does a partial cache line write-back, it attempts to recover to cache-line alignment on
the next write-back.
Note:
Software can determine if a descriptor has been used for packet reception by checking the
DD bit of the descriptor written back. Software should not use the Receive Head register as
an indication to the descriptor usage by hardware.
3.5.2.8 Receive Descriptor Queue Structure
Figure 3-23 shows the structure of each of the receive descriptor rings with each ring using a
contiguous memory space. Hardware maintains internal circular queues of 64 descriptors (per queue)
to hold the descriptors that were fetched from the software ring. The hardware writes back used
descriptors just prior to advancing the head pointer(s). Head and tail pointers wrap back to base when
size descriptors have been processed.
230