82598EB Datasheet, PDF (221/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Receive Functionality
Table 3-51. Receive Errors (RDESC.ERRORS) Layout
7
IPE
6
TCPE
5
USE
4
OSE
3
PE
2
Reserved
1
LE
0
CE
• IPE (bit 7) – IPv4 checksum error
• TCPE (bit 6) – TCP/UDP checksum error
• USE (bit 5) – Undersize error – Undersized packet received
• OSE (bit 4) – Oversize error – Oversized packet received
• PE (bit 3) – Packet error – Illegal symbol or error symbol in the middle of a received packet
• Reserved (bit 2) – Reserved
• LE (bit 1) – Length error
• CE (bit 0) – CRC error
The IP and TCP checksum error bits from Table 3-51 are valid only when the IPv4 or TCP/UDP
checksum(s) is performed on the received packet as indicated via IPCS and L4CS. These, along with the
other error bits, are valid only when the EOP and DD bits are set in the descriptor.
Note: Receive checksum errors have no effect on packet filtering.
VLAN Tag Field (16 bit offset 48)
Hardware stores additional information in the receive descriptor for 802.1q packets. If the packet type
is 802.1q (determined when a packet matches VET and VLNCTRL.VME = 1b), then the VLAN Tag field
records the VLAN information and the four-byte VLAN information is stripped from the packet data
storage. Otherwise, the VLAN Tag field contains 0x0000.
Table 3-52. VLAN Tag Field Layout (for 802.1q Packet)
15 13
12
PRI
CFI
11
0
VLAN
3.5.2.4 Advanced Receive Descriptors
Table 3-53 lists the receive descriptor.
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