82598EB Datasheet, PDF (83/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - PCIe
Table 3-15. Memory and IO Mapping
Function
LAN 0
LAN 1
Mapping
Window
Mapping Description
Memory
BAR 0
The internal registers and memories are accessed as direct memory mapped offsets from the
Base Address register. Software can access a Dword or 64 bits.
Flash
BAR 1
The external Flash can be accessed using direct memory mapped offsets from the Flash Base
Address register. Software can access byte, word, Dword or 64 bits.
I/O
BAR 2
All internal registers, memories, and Flash can be accessed using I/O operations. There are two
4-byte registers in the IO mapping window: Addr Reg and Data Reg. Software can access byte,
word or Dword.
MSI-X
BAR 3
The internal registers and memories are accessed as direct memory mapped offsets from the
Base Address register. Software can access a Dword or 64 bits.
3.1.1.14.3.1 Expansion ROM Base Address
This register is used to define the address and size information for boot-time access to optional Flash
memory. It is enabled by EEPROM words 0x24 and 0x14 for LAN 0 and LAN 1, respectively. This register
returns a zero value for functions without an expansion ROM window.
31:11
10:1
0
Expansion Rom BAR (R/W – 31:12316; 0b – 22/15:1) Refer to the previously
En
mentioned text regarding Flash BAR.
Field
En
Reserved
Address
Bit(s)
R/W
0
R/W
10:1
31:11
R
R/W
Initial
Value
Description
0b
1b = Enables expansion ROM access.
0b = Disables expansion ROM access.
0b
Always read as 0b. Writes are ignored.
0b
Read-write bits are hardwired to 0b and dependent on the memory
mapping window size. LAN Expansion ROM spaces can be either 64 kB or up
to 8 MB in the power of 2. Mapping window size is set by EEPROM word
0x0F.
Subsystem ID – This value can be loaded automatically from the EEPROM at power up with a default
value of 0x0000.
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