82598EB Datasheet, PDF (213/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Receive Functionality
Table 3-48. Queue Assignment for Received Packets
Case
1
2
3
4
Configuration
VMDq
RSS
Off
Off
Off
On
On
Off
On
On
Bit Allocation [5:0]
VMDq
RSS
None
None
None
3:0
3:0
None
5:4
3:0
Comments
Hardware default. Queue 0 used
Bits [5:4]=00b
Bits [5:4]=00b
Note:
• Case 1 – A single receive packet buffer with a single queue 0 is used for all receive traffic.
• Case 2 – A single receive packet buffer is used. RSS determines one of up to 16 queues per
receive packet
• Case 3 – A single receive packet buffer is used. VMDq determines one of up to 16 queues per
receive packet
• Case 4 – Used to separate traffic into four sets, each with 16 queues. A queue is selected as
follows:
—Bits 5:4 of the queue index are provided from bits 1:0 of the VMDq output index.
—Bits 3:0 are provided from the RSS output index. If bit 0 of the VMDq output index is 0b, then
RSS output index 0 is used. If bit 0 of the VMDq output index is 1b, then RSS output index 1 is
used.
Configuration registers (CSRs) that control queue operation are replicated per queue (total of 64 copies
of each register). Each of the replicated registers corresponds to a queue such that the 6-bit queue
index equals the serial number of the register (register 0 corresponds to queue 0, etc.). Registers
included in this category are: RDBAL[63:0] and RDBAH[63:0] – Rx Descriptor Base
• RDLEN[63:0] – RX Descriptor Length
• RDH[63:0] – RX Descriptor Head
• RDT[63:0] – RX Descriptor Tail
• RXDCTL[63:0] – Receive Descriptor Control
Configuration registers (CSRs) that define the functionality of descriptor queues are replicated per
VMDq index to allow for separate configuration in a virtualization environment (total of 16 copies of
each register). Each of the replicated registers corresponds to a set of queues with the same VMDq
index, such that the VMDq index of the queue identifies the serial number of the register. Examples:
• Case 3 above – The VMDq index defines bits [3:0] of the queue index (all 16 copies are used, one
per value of the VMDq index). Therefore, queue 0 is associated with the register indexed 0, queue
1 is associated with the register indexed 1, etc.
• Case 4 above – The VMDq index defines bits [5:4] of the queue index (only 4 copies are used,
one per value of the VMDq index). Therefore, queues 0, 1, …, 15 are associated with the register
indexed 0, queues 16, 17, …, 31 are associated with the register indexed 1, etc.
213