82598EB Datasheet, PDF (58/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - PCIe
• CSI Platforms:
—Tags are according to the CPU ID.
—Request tag = CPU ID.
3.1.1.3.2 Completion Timeout Mechanism
In any split transaction protocol, a risk is associated with the failure of a requester to receive an
expected completion. To enable requesters to attempt recovery, a completion timeout mechanism is
defined. The completion timeout mechanism is activated for each request that requires completions
when the request is transmitted. The PCIe v2.0 (2.5 GT/s) specification requires that:
• The completion timeout timer should not expire in less than 10 ms.
• The completion timeout timer must expire if a request is not completed within 50 ms.
• However, some platforms experience completion latencies longer than 50 ms (in some cases up
to seconds). The 82598 provides a programmable range for the completion timeout, as well as
the ability to disable the completion timeout. PCIe v2.0 (2.5 GT/s) specification defines that
completion timeout is programmed through an extension of the PCIe capability structure.
The 82598 controls the following aspects of completion timeout:
• Disabling or enabling completion timeout
• Disabling or enabling resending a request on completion timeout
• A programmable range of timeout values
Programming the behavior of completion timeout is done differently depending on whether capability
structure version 0x1 or capability structure version 0x2 (future extension) is enabled. Table 3-1 lists
the behavior.
Table 3-1. Completion Timeout Programming
Capability
Capability Structure Version = 0x1
Capability Structure Version = 0x2
Completion Timeout Enabling
Loaded from the EEPROM into a CSR
bit.
Controlled through PCI configuration. Visible
through a read-only CSR bit.
Resend Request Enable
Loaded from the EEPROM into a CSR
bit.
Loaded from the EEPROM into a read-only CSR
bit.
Completion Timeout Period
Loaded from the EEPROM into a CSR
bit.
Controlled through PCI configuration. Visible
through a read-only CSR bit.
3.1.1.3.2.1 Completion Timeout Enable
• Version = 0x1 – Loaded from the Completion Timeout Disable bit in the EEPROM into the
Completion_Timeout_Disable bit in the PCIe Control (GCR) register. The default is Completion
Timeout Enabled.
• Version = 0x2 – Programmed through the PCI configuration. Visible through the
Completion_Timeout_Disable bit in the PCIe Control (GCR) register. The default is: Completion
Timeout Enabled.
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