82598EB Datasheet, PDF (114/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Non-Volatile Memory (EEPROM/Flash)
Function
Command
Data Byte
Release EEPROM¹
0xC7
0xB6
1. This solution requires a controllable SMBus connection to the 82598. If more than one 82598 is in a state to accept this solution,
then all the 82598s connected to the same SMBus accepts the command. The 82598s in D0u release the EEPROM.
After receiving a release EEPROM command, firmware should keep its current state. It is the
responsibility of the programmer updating the EEPROM to send a firmware reset, if required, after the
full EEPROM update process completes.
Data byte 0xB6 is the LSB of the 82598’s default device ID.
An additional command is introduced to enable the EEPROM write directly from the SMBus interface to
enable the EEPROM modification (writing from the SMBus to any MAC CSR register). The same rules as
for the Release EEPROM command that determine when the firmware accepts this command apply to
this command as well.
The Command is sent on a fixed SMBus address of 0xC8. The format of the command is SMBus Block
Write is as follow:
Function
EEPROM
Write
Cmd
0xC8
Byte
Count
7
Data 1
Config
address 2
Data 2
Config
address 1
Data 3
Data 4
…
Config
Config data
…
address 0
MSB
Data 7
Config
data LSB
The MSB in configuration address 2 indicates which port is the target of the access (0 or 1).
The 82598 always enables the manageability block after power up. The manageability clock is stopped
if the manageability function is disabled in the EEPROM and one of the functions had transitioned to
D0a; otherwise, the manageability block gets the clock and is able to wait for the new command.
This command enables writing to any MAC CSR register as part of the EEPROM recovery process. This
command can also be used to write to the EEPROM and update different sections in it.
3.1.3.2 Flash
The 82598 provides an interface to an external serial Flash/ROM memory device. This Flash/ROM
device can be mapped into memory and/or I/O address space for each LAN device through the use of
Base Address Registers (BARs). The EEPROM bit associated with each LAN device selectively disables/
enables whether the Flash can be mapped for each LAN device by controlling the BAR register
advertisement and write ability.
3.1.3.2.1 Flash Interface Operation
The 82598 provides two different methods for software access to the Flash.
Using legacy Flash transactions, the Flash is read from, or written to, each time the host processor
performs a read or a write operation to a memory location that is within the Flash address mapping or
at boot via accesses in the space indicated by the Expansion ROM Base Address register. All accesses to
the Flash require the appropriate command sequence for the 82598 used. Refer to the specific Flash
data sheet for more details on reading from or writing to Flash.
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