82598EB Datasheet, PDF (74/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - PCIe
Unexpected
completion
• Received Completion
Without a Request For It
(Tag, ID, etc.)
Receiver Overflow
• Received TLP Beyond
Allocated Credits
Flow Control
Protocol Error
Malformed TLP
(MP)
Completion with
Unsuccessful
Completion
Status
• Minimum Initial Flow
Control Advertisements
• Flow Control Update for
Infinite Credit
Advertisement
• Data Payload Exceed
Max_Payload_Size
• Received TLP Data Size
Does Not Match Length
Field
• TD field value does not
correspond with the
observed size
• Byte Enables Violations
• PM Messages That Don’t
Use TC0
• Usage of Unsupported VC
Uncorrectable
ERR_NONFATAL
Log Header
Uncorrectable
ERR_FATAL
Uncorrectable.
ERR_FATAL
Discard TLP
Receiver Behavior is Undefined
Receiver Behavior is Undefined
Uncorrectable
ERR_FATAL
Log Header
Drop the Packet, Free FC Credits
No Action (already
done by originator of
completion)
Free FC Credits
3.1.1.12.3 Error Pollution
Error pollution can occur if error conditions for a given transaction are not isolated to the error's first
occurrence. If the PHY detects and reports a receiver error, to avoid having this error propagate and
cause subsequent errors at the upper layers, the same packet is not signaled at the data link or
transaction layers. Similarly, when the data link layer detects an error, subsequent errors that occur for
the same packet are not signaled at the transaction layer.
3.1.1.12.4 Completion With Unsuccessful Completion Status
A completion with unsuccessful completion status is dropped and not delivered to its destination. The
request that corresponds to the unsuccessful completion is retried by sending a new request for the
data.
3.1.1.12.5 Error Reporting Changes
The PCIe v2.0 (2.5 GT/s) specification defines two changes to advanced error reporting. The Role-
Based Error Reporting bit in the Device Capabilities register is set to 1b to indicate that these changes
are supported:
• Setting the SERR# Enable bit in the PCI Command register enables UR reporting (in the same
manner that the SERR# Enable bit enables reporting of correctable and uncorrectable errors). In
other words, the SERR# Enable bit overrides the UR Error Reporting Enable bit in the PCIe Device
Control register.
• Changes in the response to some uncorrectable non-fatal errors detected in non-posted requests
to the 82598. These are called Advisory Non-Fatal Error cases. For the errors listed, the following
is defined:
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