82598EB Datasheet, PDF (561/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Design Guidelines
8 Design Guidelines
This section provides recommendations for selecting components and connecting interfaces, dealing
with special pins, and some layout guidance.
Unused interfaces should be terminated with pull-up or pull-down resistors as indicated in this
datasheet or reference schematic. Note that some unused interfaces must be left open. Do not attach
pull-up or pull-down resistors to any balls identified as No Connect or Reserved No Connect. There also
are reserved pins, identified by RSVD_1P2 and RSVD_VSS that need pull-up or pull-down resistors
connected to them. The device can enter special test modes unless these strappings are in place.
8.1
Connecting the PCIe interface
The controller connects to the host system using a PCIe interface which can be configured to operate in
several link modes. These are detailed in the functional description. A link between the ports of two
devices is a collection of lanes. Each lane has to be AC-coupled between its corresponding transmitter
and receiver; with the AC-coupling capacitor located close to the transmitter side (within 1 inch). Each
end of the link is terminated on the die into nominal 100differential DC impedance. Board termination
is not required
For information on PCIe, refer to the PCI Express* Base Specification, Revision 2.0 and PCI Express*
Card Electromechanical Specification, Revision 2.0.
8.1.1 Link Width Configuration
The device supports a maximum link width of x8, x4, x2, or x1 as determined by the EEPROM
LANE_WIDTH field in the PCIe init configuration. This is loaded into the Maximum Link Width field of the
PCIe capability Register (LCAP[11:6]; with the silicon default of a x8 link).
During link configuration, the platform and the controller negotiate on a common link width. In order
for this to work, the chosen maximum number of PCIe lanes have to be connected to the host system.
8.1.2 Polarity Inversion and Lane Reversal
To ease routing, board designers have flexibility to use the different lane reversal modes supported by
the 82598. Polarity inversion can also be used since the polarity of each differential pair is detected
during the link training sequence.
When lane reversal is used, some of the down-shift options are not available. For a detailed description
of the available combinations, consult the functional description.
8.1.3 PCIe Reference Clock
The device requires a 100 MHz differential reference clock, denoted PE_CLK_P and PE_CLK_N. This
signal is typically generated on the system board and routed to the PCIe port. For add-in cards, the
clock will be furnished at the PCIe connector.
The frequency tolerance for the PCIe reference clock is +/- 300 ppm.
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