82598EB Datasheet, PDF (323/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Register Descriptions
4.4.3.4.4 Flow Control Receive Threshold High – FCRTH (0x03260 + 8*n[n=0..7];
RW)
Where each 32-bit register (n=0… 7) refers to a different receive packet buffer.
Field
Reserved
RTH[n]
Reserved
FCEN[n]
Bit(s)
Initial
Value
Description
3:0
0x0
Reserved
The underlying bits might not be implemented in all versions of the 82598.
Must be written with 0x0.
18:4
0x0
Receive Threshold High n
Receive packet buffer n FIFO high water mark for flow control transmission (16 bytes
granularity).
30:19
0x0
Reserved
Reads as 0x0
Should be written to 0x0 for future compatibility.
31
0b
Flow control enable for receive packet buffer n.
This register contains the receive threshold used to determine when to send an XOFF packet and counts
in units of bytes. The value must be at least eight bytes less than the maximum number of bytes
allocated to the receive packet buffer and the lower four bits must be programmed to 0x0 (16-byte
granularity). Each time the receive FIFO reaches the fullness indicated by RTH, hardware transmits a
pause frame if the transmission of flow control frames is enabled.
4.4.3.4.5 Flow Control Refresh Threshold Value – FCRTV (0x032A0; RW)
Field
FC_refresh_
th
Reserved
Bit(s)
Initial
Value
Description
15:0
0x0
Flow Control Refresh Threshold
This value indicates the threshold value of the flow control shadow counter. When the
counter reaches this value, and the conditions for a pause state are still valid (buffer
fullness above low threshold value), a pause (XOFF) frame is sent to link partner.
31:16 0x0
Reserved
4.4.3.4.6 Transmit Flow Control Status – TFCS (0x0CE00; RO)
Field
TXOFF
Reserved
Bit(s)
Initial
Value
Description
0
0b
Transmission Paused
Pause state indication of the transmit function when symmetrical flow control is
enabled.
7:1
0x0
Reserved
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