82598EB Datasheet, PDF (148/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Power Delivery
Table 3-41. D0a to Dr and Back Without Transition to D3
Note
1
2
3
4
5
6
7
9
10
11
12
Description
The system must assert PE_RST_N before stopping the PCIe reference clock. It must also wait t_l2clk after link
transition to L2/L3 before stopping the reference clock.
On assertion of PE_RST_N, the 82598 transitions to Dr state and the PCIe link transition to electrical idle.
The system starts the PCIe reference clock t_PWRGD-CLK before de-assertion PE_RST_N.
The internal PCIe clock is valid and stable t_ppg-clkint from PE_RST_N de-assertion.
The PCIe internal PWRGD signal is asserted t_clkpr after the external PE_RST_N signal.
Assertion of internal PCIe PWRGD causes the EEPROM to be re-read and disables wake up.
APM wake up mode can be enabled based on what is read from the EEPROM.
Link training starts after t_pgtrn from PE_RST_N de-assertion.
A first PCIe configuration access might arrive after t_pgcfg from PE_RST_N de-assertion.
A first PCI configuration response can be sent after t_pgres from PE_RST_N de-assertion.
Writing a 1b to the Memory Access Enable bit in the PCI Command register transitions the 82598 from D0u to D0
state.
3.3.1.5.4 Timing Requirements
The 82598 requires the following start-up and power-state transitions.
Table 3-42. Start-Up and Power-State Transitions
Parameter
t_xog
t_PWRGD-CLK
t_PVPGL
T_pgcfg
t_d0mem
Description
Xosc stable from power
stable
PCIe clock valid to PCIe
power good
Power rails stable to PCIe
PWRGD active
External PWRGD signal to
first configuration cycle.
Device programmed from
D3h to D0 state to next
device access
Min
Max.
10 ms
Notes
100 s
-
According to PCIe specification.
100 ms -
According to PCIe specification.
100 ms
According to PCIe specification.
10 ms
According to PCI power management
specification.
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