82598EB Datasheet, PDF (118/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Network Interface
• 1 GbE backplane
• Ethernet KX (802.3ap)
• Ethernet BX (PICMG3.1)
• 10 GbE backplane
• Ethernet KX4 (802.3ap)
The analog interface is configured to the appropriate electrical specification mode (according to the
configuration specified in the EEPROM/AUTOC). Additional analog configuration to the core block is also
possible.
3.1.4.3.2 MAC Link Setup and Auto Negotiation
The MAC block in the 82598 supports both 10 Gb/s and 1 Gb/s link modes and the appropriate
functionality specified in the standards for these link modes.
Each of these link modes can use different PMD sub-layer and base band medium types.
In 10 Gb/s, there's also support for 10 Gb/s Attachment Unit Interface (XAUI).
Which of these link speeds is used can be determined through static configuration (Force) or Auto
Negotiation, as defined in 802.3ap specification clause 73, the auto negotiation process defined in the
specification enables the choosing between KX4 (10G) and KX (1G) types.
The 82598 also supports the 1 Gb/s auto negotiation as defined in 802.3 specification clause 37 to
support the auto negotiation function when configured to work as Ethernet BX (PICMG).
Link setting is done by configuring the speed configuration and auto negotiation in AUTOC.LMS and
restarting auto negotiation by setting AUTOC.RestartAN to 1b.
3.1.4.3.3 Hardware Detection of Non-Auto Negotiation Partner
The 82598 also supports parallel detection. Parallel detection is available in parallel to auto negotiation
to determine the link mode (KX4 or KX) by activating KX4 and KX alternately and trying to achieve a
sync indication from the related PCS this is done as part of the Auto Negotiation to enable link with
legacy devices (that do not support Auto Negotiation).
3.1.4.4 MDIO/MDC
3.1.4.4.1 MDIO Direct Access
The Management Data Interface is accessed through registers MSCA and MSRWD. A single
management frame is sent by setting bit MSCA.30 to logic 1 and this bit is auto cleared when the frame
is done. For old format write operations, the data for the write is first set up in register MSRWD bits
15:0. The next step is to initialize register MSCA with the appropriate control information (start, op
code, etc.) and with bit 30 set to logic 1. Bit 30 is reset to logic 0b when both the frame is complete.
The steps for old format read operations is identical except that the data in address MSRWD bits (15:0)
is ignored and the data read from the external device is stored in register MSRWD bits (31:16). New
format operations must be performed in two steps. The address portion of the pair of frames is sent by
setting register MSCA bits (15:0) to the desired address, bits (29:28) to 00b which is the start code
that identifies new format, and bits (27:26) to 00b which specifies the address portion of the new frame
format. A second data frame must be sent after the address frame completes. This second frame is like
the old format reads and writes for Op Codes 01b and 10b. Another Op Code of 11b is defined which
acts like a read operation except that the external device provides the read data from the register
pointed to by the last new format address it used and then the address is incremented.
The output MNG_MDI_INPROG goes high if enabled using register MSCA bit 31 when the command is
written to register MSCA bit 30. It stays high until the management frame is complete.
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