82598EB Datasheet, PDF (345/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Register Descriptions
4.4.3.7.2 Transmit Descriptor Base Address High – TDBAH (0x06004 +
n*0x40[n=0..31]; RW)
Field
TDBAH
Bit(s)
Initial
Value
Description
31:0
X
Transmit Descriptor Base Address [63:32]
This register contains the upper 32 bits of the 64-bit descriptor base address.
4.4.3.7.3 Transmit Descriptor Length – TDLEN (0x06008 + n*0x40[n=0..31];
RW)
Field
0
LEN
Reserved
Bit(s)
Initial
Value
Description
6:0
0x0
Ignore on write. Reads back as 0x0.
19:7
0x0
Descriptor Length
31:20
0x0
Reads as 0x0. Should be written to 0x0.
This register contains the descriptor length and must be 128-byte aligned.
4.4.3.7.4 Transmit Descriptor Head – TDH (0x06010 + n*0x40[n=0..31]; RO)
Field
TDH
Reserved
Bit(s)
Initial
Value
Description
15:0
0x0
Transmit Descriptor Head
31:16
0x0
Reserved. Should be written with 0x0.
This register contains the head pointer for the transmit descriptor ring. It points to a 16-byte datum.
Hardware controls the pointer. The only time that software should write to this register is after a reset
(hardware reset or CTRL.RST) and before enabling the transmit function (TXDCTL.ENABLE).
If software writes to this register while the transmit function is enabled, on-chip descriptor buffers
might be invalidated and hardware behavior might be indeterminate.
4.4.3.7.5 Transmit Descriptor Tail – TDT (0x06018 + n*0x40[n=0..31]; RW)
Field
Bit(s)
Initial
Value
Description
345