82598EB Datasheet, PDF (120/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Network Interface
• Set the TXOFF bit in the TFCS Register
• Initialize the pause timer based on the packet's Pause Timer field
• Disable packet transmission or schedule the disabling of transmission after the current packet
completes.
Resuming transmission might occur under the following conditions:
• Expiration of the pause timer
• Reception of on XON frame (a frame with its pause timer set to 0b)
Both conditions clear the TXOFF status bit in the Transmit Flow Control Status register and transmission
can resume. Hardware records the number of received XON frames.
3.1.4.5.2 Discard Pause Frames and Pass MAC Control Frames
Two bits in the Receive Control register are implemented specifically for control over receipt of pause
and MAC control frames. These bits are Discard PAUSE Frames (DPF) and Pass MAC Control Frames
(PMCF).
The DPF bit forces the discarding of any valid pause frame addressed to the device's station address. If
the packet is a valid pause frame and is addressed to the station address (receive address [0]), the
device does not pass the packet to host memory if the DPF bit is set to logic high. However, if a flow
control packet is sent to the station address, and is a valid flow control frame, it is transferred when
DPF bit is set to 0b. This bit has no affect on pause operation, only the DMA function.
The PMCF bit allows for the passing of any valid MAC control frames to the system, which does not have
a valid pause opcode. In other words, the frame must have the correct MAC control frame multicast
address (or the MAC station address), but does not have the defined pause opcode of 0x0001. Frames
of this type are DMA'd to host memory when PMCF is logic high.
3.1.4.5.3 Transmission of Pause Frames
Similar to the reception flow control packets mentioned above, XOFF packets might be transmitted only
if this configuration has been negotiated between the link partners via the auto negotiation process. In
other words, the setting of this bit by the driver indicates the desired configuration.
The content of the Flow Control Receive Threshold High register determines at what point hardware
transmits first a PAUSE frame. Hardware monitors the fullness of the receive FIFO and compares it with
the contents of FCRTH. When the threshold is reached, hardware sends a pause frame with its pause
time field equal to FCTTV.
At this time, the hardware starts counting an internal shadow counter (reflecting the pause timeout
counter at the partner end) from zero. When the counter reaches the value indicated in FCRTV register,
then, if the PAUSE condition is still valid (meaning that the buffer fullness is still above the low
watermark), an XOFF message is sent again.
Once the receive buffer fullness reaches the low water mark, hardware sends an XON message (a
pause frame with a timer value of zero). Software enables this capability with the XONE field of the
FCRTL.
Hardware sends a pause frame if it has previously sent one and the FIFO overflows. This is intended to
minimize the amount of packets dropped if the first pause frame did not reach its target.
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