82598EB Datasheet, PDF (325/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Register Descriptions
This register contains the upper 32 bits of the 64-bit descriptor base address.
4.4.3.5.3 Receive Descriptor Length – RDLEN (0x01008 + 0x40*n[n=0..63]; RW)
Field
0
LEN
Reserved
Bit(s)
Initial
Value
6:0
0x0
19:7
0x0
31:20
0x0
Description
Ignore on write. Reads back as 0x0.
Descriptor Length.
Reads as 0x0. Should be written to 0 for future compatibility.
This register sets the number of bytes allocated for descriptors in the circular descriptor buffer. It must
be 128-byte aligned.
4.4.3.5.4 Receive Descriptor Head – RDH (0x01010 + 0x40*n[n=0..63]; RO)
Field
RDH
Reserved
Bit(s)
Initial
Value
15:0
0x0
31:16
0x0
Description
Receive Descriptor Head
Reserved. Should be written with 0x0.
This register contains the head pointer for the receive descriptor buffer. The register points to a 16-byte
datum. Hardware controls the pointer. The only time that software should write to this register is after
a reset (hardware reset or CTRL.RST) and before enabling the receive function (RXCTRL.RXEN).
4.4.3.5.5 Receive Descriptor Tail – RDT (0x01018 + 0x40*n[n=0..63]; RW)
Field
RDT
Reserved
Bit(s)
Initial
Value
15:0
0x0
31:16
0x0
Description
Receive Descriptor Tail
Reads as 0x0. Should be written to 0x0 for future compatibility.
This register contains the tail pointers for the receive descriptor buffer. The register points to a 16-byte
datum. Software writes the tail register to add receive descriptors to the hardware free list for the ring.
Note:
If the 82598 uses the packet-split feature, software should write an even number to the tail
register. The tail pointer should be set to point one descriptor beyond the last empty
descriptor in host descriptor ring.
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