82598EB Datasheet, PDF (219/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Receive Functionality
Although alignment is completely unrestricted, it is highly recommended that software allocate receive
buffers on at least cache-line boundaries whenever possible.
Note: When the No-Snoop Enable bit is used in advanced descriptors, the buffer address should
always be 16-bit aligned.
3.5.2.3 Legacy Receive Descriptor Format
A receive descriptor is a data structure that contains the receive data buffer address and fields for
hardware to store packet information. If SRRCTL[n],DESCTYPE = 000b, the 82598 uses the Legacy Rx
Descriptor as listed in Table 3-49. The shaded areas indicate fields that are modified by hardware upon
packet reception (called descriptor write-back).
Table 3-49. Legacy Receive Descriptor (RDESC) Layout
63
48 47
40 39
32 31
16 15
0
0
Buffer Address [63:0]
8
VLAN Tag
Errors
Status 0
Fragment Checksum¹
Length
1. The checksum indicated here is the unadjusted 16-bit ones complement of the packet. A software assist might be required to back
out appropriate information prior to sending it up to upper software layers. The fragment checksum is always reported in the first
descriptor (even in the case of multi-descriptor packets).
Length Field (16 bit offset 0)
After receiving a packet for the 82598, hardware stores the packet data into the indicated buffer and
writes the length, status, errors, and status fields. Length covers the data written to a receive buffer
including CRC bytes (if any). Software must read multiple descriptors to determine the complete length
for packets that span multiple receive buffers.
Fragment Checksum (16 bit offset 16)
This field is used to provide the fragment checksum value.
Status 0 Field (8 bit offset 32)
Status information indicates whether the descriptor has been used and whether the referenced buffer is
the last one for the packet. Refer to Table 3-50 for the layout of the status field. Error status
information is shown in Table 3-51.
Table 3-50. Receive Status 0 (RDESC.STATUS-0) Layout
7
6
5
4
3
2
1
PIF
IPCS
L4CS
UDPCS
VP
Reserved
EOP
• PIF (bit 7) – Passed in-exact filter
• IPCS (bit 6) – IPv4 checksum calculated on packet
• L4CS (bit 5) – L4 checksum calculated on packet
• UDPCS (bit 4) – UDP/TCP checksum calculated on packet
0
DD
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