82598EB Datasheet, PDF (231/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Receive Functionality
Figure 3-23. Receive Descriptor Ring Structure
Software inserts receive descriptors by advancing the tail pointer(s) to refer to the address of the entry
just beyond the last valid descriptor. This is accomplished by writing the descriptor tail register(s) with
the offset of the entry beyond the last valid descriptor. The hardware adjusts its internal tail pointer(s)
accordingly. As packets arrive, they are stored in memory and the head pointer(s) is incremented by
hardware. When the head pointer(s) is equal to the tail pointer(s), the queue(s) is empty. Hardware
stops storing packets in system memory until software advances the tail pointer(s), making more
receive buffers available.
The receive descriptor head and tail pointers reference to16-byte blocks of memory. Shaded boxes in
the figure represent descriptors that have stored incoming packets but have not yet been recognized by
software. Software can determine if a receive buffer is valid by reading descriptors in memory rather
than by IO reads. Any descriptor with a non-zero status byte has been processed by the hardware, and
is ready to be handled by the software.
Note:
The head pointer points to the next descriptor that is written back. At the completion of the
descriptor write-back operation, this pointer is incremented by the number of descriptors
written back. Hardware owns all descriptors between [head .. tail]. Any descriptor not in this
range is owned by software.
The receive descriptor rings are described by the following registers:
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