82598EB Datasheet, PDF (143/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Power Delivery
• ACPI PME is disabled for all PCI functions
Entry into Dr Disable is done on assertion of PCIe PE_RST_N. It might also be possible to enter Dr
Disable mode by reading the EEPROM while already in Dr state. The usage model for this later case is
on system power up, assuming that manageability and wake up are not required. Once the 82598
enters Dr state on power-up, the EEPROM is read. If the EEPROM contents determine that the
conditions to enter Dr Disable are met, the 82598 then enters this mode (assuming that PCIe
PE_RST_N is still asserted).
Exit from Dr Disable is through de-assertion of PCIe PE_RST_N.
If Dr Disable mode is entered from D3 state, the 82598 asserts the DEV_PWRDN_N output signal to
indicate to the platform that it might remove power from the 82598. The platform must remove all
power rails from the 82598 if it needs to use this capability. Exiting from this state is through power-up
reset to the 82598. Note that the state of the DEV_PWRDN_N and the PHYx_PWRDN_N outputs is
undefined once power is removed from the 82598.
3.3.1.4.4.2 Entry to Dr State
Dr entry on platform power-up is as follows:
• Asserting Internal Power On Reset or LAN_PWR_GOOD. The 82598 power is kept to a minimum
by keeping the XAUI interfaces in low power.
• The EEPROM is then read and determines the 82598 configuration.
• If the APM Enable bit in the EEPROM's Initialization Control Word 2 is set then APM wake up is
enabled (for each port independently).
• If the MNG Enable bit in the EEPROM is set, pass-through manageability is not enabled.
• Each of the LAN ports can be enabled, if required, for WoL or manageability. See
Section 3.3.1.3.2 for exact condition to enable a port.
• The PCIe link is not enabled in Dr state following system power up (since PE_RST_N is asserted).
Entry to Dr state from D0a state is through assertion of the PE_RST_N signal. An ACPI transition to the
G2/S5 state is reflected in an 82598 transition from D0a to Dr state. The transition might be orderly
(programmer selected a show down operating system option), in which case the software device driver
might have a chance to intervene. Or, it might be an emergency transition (power button override), in
which case, the software device driver is not notified.
Transition from D3 state to Dr state is done by assertion of PE_RST_N signal. Prior to that, the system
initiates a transition of the PCIe link from L1 state to either the L2 or L3 state (assuming all functions
were already in D3 state). The link enters L2 state if PCI-PM PME is enabled.
3.3.1.5 Timing of Power-State Transitions
The following sections give detailed timing for the state transitions. In the diagrams the dotted
connecting lines represent the 82598 requirements, while the solid connecting lines represent the
82598 guarantees.
The timing diagrams are not to scale. The clocks edges are shown only to indicate running clocks are
not used to indicate the actual number of cycles for any operation.
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