82598EB Datasheet, PDF (277/596 Pages) Intel Corporation – Intel® 82598EB 10 Gigabit Ethernet Controller Datasheet

Intel^® 82598EB 10 GbE Controller - Interrupts
The 82598 implements eight entries, software programmable, table of TCP ports and eight registers
with control bits filter and size threshold. In addition, a dedicated register enables setting of VLAN
priority threshold. If a packet is received on one of these TCP ports, and the conditions set by the
register fit to the packet, Hardware should interrupt immediately, overriding the interrupt moderation
by the EITR counter.
A Port Enabling bit allows enabling or disabling of a specific port for this purpose.
3.5.4.4.1 Implementation
The logic of the dynamic interrupt moderation is as follows:
• There are eight port filters. Each filter checks the value of incoming packets TCP port, size and
control bits, against values stored in filter's register. Each parameter can be bypassed (or wild
carded). Each filter can be enabled or disabled. If one of the filters detects an adequate packet,
an immediate interrupt is issued.
• When VLAN priority filtering is enabled, VLAN packets trigger an immediate interrupt when the
VLAN priority is equal to or above the VLAN priority threshold. This is regardless of the status of
the port filters.
Note that EITR is reset to 0b following a dynamic interrupt.
Note: Packets that are dropped or have errors do not cause an immediate interrupt.
3.5.4.5 TCP Timer Interrupt
In order to implement TCP timers for I/OAT, software needs to take action periodically (every 10 ms).
The software device driver must rely on software-based timers, whose granularity can change from
platform to platform. This software timer generates a software NIC interrupt, which then enables the
software device driver to perform timer functions as part of its usual DPC, avoiding cache thrash and
enabling parallelization. The timer interval is system-specific.
The software device driver programs a timeout value (usual value of 10 ms), and each time the timer
expires, hardware sets a specific bit in the EICR. When an interrupt occurs (due to normal interrupt
moderation schemes), software reads the EICR and discovers that it needs to process timer events
during that DPC.
The timeout should be programmable by the software device driver, and it should be able to disable the
timer interrupt if it is not needed.
3.5.4.5.1 Description
A stand-alone down-counter is implemented. An interrupt is issued each time the value of the counter
is zero.
Software is responsible for setting the initial value for the timer in the Duration field. Kick-starting is
done by writing 1b to the KickStart bit.
Following kick-starting, an internal counter is set to the value defined by the Duration field. Then the
counter is decreased by one each ms. When the counter reaches zero, an interrupt is issued. The
counter re-starts counting from its initial value if the Loop field is set.
3.5.4.6 MSI-X Interrupts
MSI-X defines a separate optional extension to basic MSI functionality. Compared to MSI, MSI-X
supports a larger maximum number of vectors per function, the ability for software to control aliasing
when fewer vectors are allocated than requested, plus the ability for each vector to use an independent
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